Method for generating memory addresses for testing memory devices
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United States of America Patent
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Nov 19, 2002
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N/A
app pub date -
Aug 3, 2000
filing date -
May 22, 1998
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Abstract
A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate memory addresses for functional testing of the memory cells within the memory device.
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