Memory array with two-phase bit line precharge
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United States of America Patent
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Apr 8, 2014
Grant Date -
Oct 25, 2012
app pub date -
Apr 19, 2011
filing date -
Apr 19, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line.
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