Method and apparatus of interleaving memory bank in multi-layer bus system
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United States of America Patent
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May 13, 2008
Grant Date -
Aug 18, 2005
app pub date -
Feb 9, 2005
filing date -
Feb 13, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating control signals, and a controller receiving the control signals generated from the plurality of slave interface units and generating signals required to access the memory banks. Accordingly, it is possible to greatly reduce a delay time caused when accessing a synchronous dynamic random access memory (SDRAM), for example, in a multi-layer bus system.
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