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Abstract

A method for detecting lack of synchronism during high level simulation of VLSI designs in which asynchronous clock domains (100 and 110) must coexist, which does not require knowledge of hardware target technology delays, and can be carried out by a small computer. The circuit design simulator is adapted to apply a value (A) representative of an unstable state to clock domain interface outputs (O'.sub.1) at each pulse of the clocks (clock 1) associated to clock domains used as interface inputs (100), during a predetermined time (T.sub.A). Thus, even though unstable states are very short regarding the clock periods and so are very difficult to detect in simulation, the method of the invention allows for detection of all potential synchronism failures. When sampling the value representative of an unstable state, the simulator may forewarn the user, store information and/or launch a standard local static analysis to determine whether or not the detected potential synchronism failure is a circuit design bug.

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First Claim