Memory circuit with increased operating speed
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United States of America Patent
Stats
-
Nov 10, 1981
Grant Date -
N/A
app pub date -
Oct 31, 1979
filing date -
Nov 24, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.
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