Memory with programmable refresh order and stagger time

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11967353
SERIAL NO

17949836

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Abstract

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Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alexander, Kyle Boise, US 6 8
Bell, Debra M Boise, US 100 1060
Johnson, Vaughn N Boise, US 5 8
Pecha, Brian T Boise, US 5 8
Wiscombe, Miles S Boise, US 13 25

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