Processor employing a power managing mechanism and method of saving power for the same
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United States of America Patent
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Jul 8, 2008
Grant Date -
Jan 11, 2007
app pub date -
Jul 8, 2005
filing date -
Jul 8, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.
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