Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers

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United States of America Patent

PATENT NO 10481976
APP PUB NO 20190121692A1
SERIAL NO

15855866

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.

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Patent Owner(s)

  • SPIN MEMORY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Berger, Neal Cupertino, US 73 1308
Crudele, Lester Tomball, US 22 467
El-Baraji, Mourad Fremont, US 17 611
Louie, Benjamin Fremont, US 83 1163

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