Enhanced floating-point unit for extended functions

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United States of America Patent

PATENT NO 7676535
APP PUB NO 20070073798A1
SERIAL NO

11236984

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Abstract

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An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exponents. A FP multiply-add (MAD) unit performs a multiply-and-add operation on the intermediate argument, a second argument, and a third argument to produce a result having a result mantissa and a result exponent. The second and third arguments have second and third mantissas and exponents, respectively.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Donofrio, David D Benicia, US 6 79
Li, Xuye Folsom, US 2 8

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