Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same
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United States of America Patent
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Feb 16, 2010
Grant Date -
May 15, 2008
app pub date -
Nov 13, 2006
filing date -
Nov 13, 2006
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Abstract
The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.
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