Method to increase strain enhancement with spacerless FET and dual liner process
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 4, 2010
Grant Date -
May 17, 2007
app pub date -
Nov 14, 2005
filing date -
Nov 14, 2005
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully