RRAM write using a ramp control circuit

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United States of America Patent

PATENT NO 10998044
SERIAL NO

16462721

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Abstract

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An RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

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Patent Owner(s)

  • HEFEI RELIANCE MEMORY LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Haukness, Brent Monte Sereno, US 55 377
Lu, Zhichao San Jose, US 47 101

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