Semiconductor memory device allowing test regardless of spare cell arrangement
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United States of America Patent
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Oct 19, 1999
Grant Date -
N/A
app pub date -
Jul 13, 1998
filing date -
Jan 19, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory device according to the present invention includes a block determining portion determining a difference in arrangement between a normal cell and a spare cell which replaces it, a data scramble controlling circuit generating a scramble ON signal when a normal cell is replaced by a spare cell and the spare cell stores inverted data, a scramble circuit inverting data to be written in response to the scramble ON signal, and a scramble circuit inverting data to be read in response to the scramble ON signal.
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