3D DRAM memory devices and structures with control circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 7, 2023
Grant Date -
Oct 12, 2023
app pub date -
Jun 5, 2023
filing date -
Oct 10, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the plurality of first memory arrays includes a plurality of first DRAM (Dynamic Random Access Memory) cells, and where the plurality of second memory arrays includes a plurality of second DRAM (Dynamic Random Access Memory) cells.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully