Low voltage trigger and save area electrostatic discharge device
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United States of America Patent
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Sep 4, 2007
Grant Date -
Mar 1, 2007
app pub date -
Aug 29, 2005
filing date -
Aug 24, 2005
priority date (Note) -
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Abstract
Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD regions are disposed between the N+ implant regions, and pocket implants underlie each of the NLDD regions. Current discharge paths are defined by corresponding NLDD regions and pocket implants when a voltage of the first node exceeds a breakdown voltage. In a specific embodiment, the breakdown voltage is less than a breakdown voltage for a logic gate oxide.
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