Multi-bit silicon nitride charge-trapping non-volatile memory cell
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United States of America Patent
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May 24, 2005
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app pub date -
Sep 18, 2002
filing date -
Sep 18, 2002
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Abstract
A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide/nitride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.
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