Importance

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Abstract

A fast Fourier transform (FFT) processor is constructed using discrete Fourier transform (DFT) butterfly modules having, in preferred example embodiments, sizes greater than 4. In a first example embodiment, the FFT processor employs size-8 butterflies. In a second example embodiment, the FFT processor employs size-16 butterflies. In addition, low power, fixed coefficient multipliers are employed to perform nontrivial twiddle factor multiplications in each butterfly module. The number of different, nontrivial twiddle factor multipliers is reduced by separating trivial and nontrivial twiddle factors and by taking advantage of twiddle factor symmetries in the complex plane and/or twiddle factor decomposition. In accordance with these and other factors, the present invention permits construction of an FFT processor with minimal power and IC chip surface area consumption.

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First Claim