Method and apparatus for indicating the severity of a fault within a computer system
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United States of America Patent
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Jan 21, 1997
Grant Date -
N/A
app pub date -
Mar 1, 1995
filing date -
Mar 1, 1995
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method and apparatus for efficiently identifying and indicating the severity of the fault within a computer system. In an exemplary embodiment of the present invention, the circuitry of a computer system may be divided into a number of groups. Each group may contain circuitry which may result in the same fault type. For example, predetermined circuitry which, when a fault is detected therein, may have a minimal affect on the normal operation of the computer system may be provided in a first group. Similarly, predetermined circuitry which, when a fault is detected therein, may have an immediate affect on the normal operation of the computer system may be provided in a second group. Each group may provide an error priority signal to a support controller. The support controller may interpret the number of error priority signals provided by the number of groups and may determine the appropriate time to take corrective action thereon.
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