Method for clock control of clocked half-rail differential logic with sense amplifier and shut-off
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United States of America Patent
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-
Aug 31, 2004
Grant Date -
Apr 15, 2004
app pub date -
Oct 15, 2002
filing date -
Oct 15, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or 'dip' experienced by prior art half-rail differential logic circuits and is therefore more power efficient.
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