Column redundancy system and method for embedded DRAM devices with multibanking capability
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United States of America Patent
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Apr 22, 2003
Grant Date -
Apr 10, 2003
app pub date -
Oct 5, 2001
filing date -
Oct 5, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A column redundancy system is disclosed for a memory array having a page structure organized into columns and data lines. In an exemplary embodiment of the invention, the system includes a steering logic network for coupling a memory input/output (I/O) device to the memory array. A storage register is in communication with the steering logic network, the storage register for storing location information for defective data lines in the memory array. During a memory operation, the location information stored in the storage register is transmitted to the steering logic network, the storage register further having the location information loaded therein prior to the memory operation. Thereby, the steering logic network prevents any of the defective data lines from being coupled to the I/O device.
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