Damascene interconnect structure with cap layer
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United States of America Patent
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Aug 21, 2007
Grant Date -
Jun 8, 2006
app pub date -
Dec 3, 2004
filing date -
Dec 3, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.
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