Synchronous first-in/first-out block memory for a field programmable gate array
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United States of America Patent
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Jan 4, 2005
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app pub date -
May 28, 2003
filing date -
May 28, 2003
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Abstract
The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.
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