ESD protection circuit for a mixed-voltage semiconductor device
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United States of America Patent
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Apr 22, 2008
Grant Date -
Mar 6, 2008
app pub date -
Aug 26, 2006
filing date -
Aug 26, 2006
priority date (Note) -
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Abstract
An ESD protection circuit is implemented for a semiconductor device having a first circuit system operating with a first power supply voltage and a first complementary power supply voltage, and a second circuit system operating with a second power supply voltage and a second complementary power supply voltage. The ESD protection circuit includes a first diode having an anode coupled to the first power supply voltage and a cathode coupled to a first node connecting the first circuit system and the second circuit system for preventing a crosstalk of current between the first power supply voltage and the second complementary power supply voltage. A first MOS transistor module is coupled between the first node and the first complementary power supply for selectively creating a current path from the first node to the first complementary supply voltage for dissipating an ESD current during an ESD event.
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