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Abstract

An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

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First Claim