Hardware compatibility circuit for a new processor architecture
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United States of America Patent
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Mar 9, 1999
Grant Date -
N/A
app pub date -
Mar 31, 1997
filing date -
Mar 31, 1997
priority date (Note) -
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Abstract
A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently executes old software code by providing the processor with a compatibility circuit which receives old software code instructions from a secondary memory, groups these instructions according the new instruction set architecture and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.
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