Method for manufacturing a semiconductor protection element and a semiconductor device
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United States of America Patent
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Sep 18, 2007
Grant Date -
Jun 15, 2006
app pub date -
Feb 6, 2006
filing date -
Mar 12, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor protection element is provided in which no heat generation occurs in a concentrated manner, in a region having a high resistance value even when electrostatic discharge (ESD) is applied, without an increase in an area of the semiconductor device. The semiconductor protection element is made up of an N-type well, P-type semiconductor substrate having a pair of N+ diffusion layers each having an impurity concentration being higher than that of the N-type well, and a silicide layer partially formed on each of the two N+ diffusion layers. The N-type well has a first exposed region being exposed on the semiconductor substrate and the silicide layer is so formed that a part of each of the two N+ diffusion layers has a second exposed region being exposed successively so as to be in contact with the first exposed region. The first exposed region is sandwiched by two N+ diffusion layers.
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