MOS transistors having recessed channel regions and methods of fabricating the same
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United States of America Patent
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-
Jul 6, 2010
Grant Date -
Aug 28, 2008
app pub date -
Dec 17, 2007
filing date -
Feb 23, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A MOS transistor having a recessed channel region is provided. A MOS transistor includes a source region and a drain region disposed in an active region of a semiconductor substrate and spaced apart from each other. A gate trench structure is disposed in the active region between the source and drain regions. A gate electrode is disposed in the gate trench structure. A gate dielectric layer is interposed between the gate trench structure and the gate electrode. A semiconductor region is disposed between the gate trench structure and the gate dielectric layer. The semiconductor region is formed of a different material from the active region. A method of fabricating the MOS transistor having a recessed channel region is also provided.
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