Importance

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Abstract

Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO.sub.2 on a top surface of a silicon wafer and a trench layer of SiO.sub.2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.

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First Claim