Flip chip package with reduced number of package layers
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United States of America Patent
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Nov 11, 1997
Grant Date -
N/A
app pub date -
Mar 20, 1996
filing date -
Mar 20, 1996
priority date (Note) -
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Abstract
A flip chip substrate includes first and second conductive layers, and a dielectric layer interposed therebetween. Each conductive layer includes a repeating pattern of a group of I/O signal traces such as two I/O signal traces, followed by a wider power or ground trace. The I/O traces on one conductive layer lie atop or below power or ground traces on the other conductive layer. The wider power and ground traces provide shielding on either side of the I/O trace group, as well as above or below.
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