High speed data bit latch circuit
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United States of America Patent
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Mar 20, 2007
Grant Date -
N/A
app pub date -
Oct 20, 2005
filing date -
Oct 20, 2005
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s1, a NAND circuit having a first input connected to signal s1, a second input connected to the clock signal, and an output signal s2, an OR circuit having a first input connected to the data input, a second input connected to s2, and an output signal s3, and a FLIP-FLOP circuit whose first input is connected to s2, whose second input connected to s3, and whose output is OUT Q.
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