Interlevel dielectric fabrication process
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United States of America Patent
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Jan 24, 1989
Grant Date -
N/A
app pub date -
Oct 31, 1985
filing date -
Oct 31, 1985
priority date (Note) -
Expired
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Abstract
A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.
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