Ferroelectric memory with amplification between sub bit-line and main bit-line
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United States of America Patent
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Jun 8, 2010
Grant Date -
Nov 1, 2007
app pub date -
Apr 24, 2007
filing date -
Apr 26, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.
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