Multi-segmented bus and method of operation
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United States of America Patent
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Nov 4, 1997
Grant Date -
N/A
app pub date -
Mar 1, 1993
filing date -
Mar 6, 1990
priority date (Note) -
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Abstract
A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.
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