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United States of America Patent
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Jan 18, 2011
Issued Date -
N/A
app pub date -
Apr 15, 2005
filing date -
Apr 30, 2004
priority date (Note) -
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Abstract
A current mirror arrangement comprising two transistors (11, 12) which are of different conductivity types and are each suitable for outputting a bias current (PBIAS, NBIAS) is specified. A controlled current source (13, 13') is connected between the two transistors (11, 12) and forms the output of a current mirror (18, 13'). The proposed principle ensures that the output bias signals (PBIAS, NBIAS) match one another in a highly precise manner. The proposed current mirror arrangement may preferably be integrated using CMOS circuit technology.
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