System, method and computer program product for designing connecting terminals of semiconductor device
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United States of America Patent
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Apr 1, 2008
Grant Date -
Oct 18, 2007
app pub date -
Jul 11, 2003
filing date -
Jul 12, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged, a first connecting net generator configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip, a second connecting net generator configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base, and a verifier configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.
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