Method of erasing a memory including first and second erase modes
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United States of America Patent
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Aug 27, 2013
Grant Date -
Oct 25, 2012
app pub date -
Jun 28, 2012
filing date -
Mar 25, 2009
priority date (Note) -
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Abstract
A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
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