Technique for reducing via capacitance
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United States of America Patent
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Apr 17, 2007
Grant Date -
Jun 22, 2006
app pub date -
Dec 16, 2004
filing date -
Dec 16, 2004
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A technique for reducing via capacitance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for reducing via capacitance. The method may comprise forming, in a circuit board, a via hole that bridges a first trace and a second trace. The method may also comprise forming a channel in a sidewall of the via hole. The method may further comprise filling the via hole and the channel with a conductive material. The method may additionally comprise removing the conductive material from the via hole without depleting the channel, thereby forming an interconnect that couples the first trace to the second trace.
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