System clock synchronization using phase-locked loop
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United States of America Patent
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Jun 28, 2005
Grant Date -
Dec 12, 2002
app pub date -
Jul 25, 2002
filing date -
Jan 3, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus for synchronizing the system clocks of wireless devices in a digital communications system is presented. A digital phase-locked loop is employed. The phase-locked loop may include a counter which is incremented by a local device system clock and latched by a frame synchronization marker received from a remote device, whereby the counter output comprises a feed forward signal. The phase-locked loop may alternatively include a counter that reflects the level of data stored in receive and/or transmit FIFO buffers. The loop output signal controls the frequency of the system clock oscillator.
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