Memory compaction management in memory devices

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United States of America Patent

PATENT NO 11934266
APP PUB NO 20230393938A1
SERIAL NO

17859468

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Abstract

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Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.

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Patent Owner(s)

  • MICRON TECHNOLOGY INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fitzpatrick, James Laguna Niguel, US 129 1883
Kaynak, Mustafa N San Diego, US 144 393
Khayat, Patrick San Diego, US 3 5
Muchherla, Kishore Kumar Fremont, US 268 692
Parthasarathy, Sivagnanam Carlsbad, US 225 1001
Ratnam, Sampath San Jose, US 48 344
Rayaprolu, Vamsi Pavan Santa Clara, US 163 249
Wu, Jiangang Milpitas, US 57 97

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