Decoding circuit for functional block
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United States of America Patent
Stats
-
Nov 20, 1990
Grant Date -
N/A
app pub date -
Jun 14, 1988
filing date -
Jun 16, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.
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