Memory apparatus and semiconductor system including the same

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11942173
APP PUB NO 20220336035A1
SERIAL NO

17473299

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Abstract

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A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.

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Patent Owner(s)

  • SK HYNIX INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Choi, Heeeun Icheon-si, KR 2 0
Jeong, Yeong Han Icheon-si, KR 4 0

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