Direct vectored legacy instruction set emulation
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United States of America Patent
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Mar 21, 2000
Grant Date -
N/A
app pub date -
Jan 5, 1998
filing date -
Jan 5, 1998
priority date (Note) -
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Abstract
A method and apparatus for emulating instructions of one microprocessor ('legacy instructions') with instructions of another microprocessor with an incompatible instruction set which provides increased throughput relative to known emulation systems. In particular, the legacy instructions are translated into direct vectors to software routines for each legacy instruction. Rather than fetching the legacy instruction and interpreting the instruction in software, the emulation system and method in accordance with the present invention fetches the direct vectors to the software routines which emulate the legacy instructions. The legacy instructions can either be translated by way of software when the legacy memory is loaded or modified, or by way of hardware when legacy memory is accessed. By fetching the direct vectors, the need for software-based look-up tables for interpreting the legacy instructions is obviated. As such, the probability of cache misses is greatly reduced which increases the throughput of the system.
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