Layered chip package and method of manufacturing same
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United States of America Patent
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Jun 21, 2011
Grant Date -
Feb 25, 2010
app pub date -
Aug 20, 2008
filing date -
Aug 20, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.
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