On-chip PLL locked frequency determination method and system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 10, 2005
Grant Date -
Apr 22, 2004
app pub date -
Oct 22, 2002
filing date -
Oct 22, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully