Tamper barrier for electronic device
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United States of America Patent
Stats
-
Feb 20, 2007
Grant Date -
Jul 28, 2005
app pub date -
Jun 15, 2004
filing date -
Jan 23, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A tamper protected printed circuit board assembly including a printed circuit board and a partially enveloping tamper wrap covering the entirety of the top surface of the printed circuit board and a first portion of the bottom surface of the printed circuit board, wherein a second portion of the bottom surface of the printed circuit board is not covered by the tamper wrap is provided. The printed circuit board includes two security trace layers each having two security traces thereon, preferably in a serpentine pattern. The tamper wrap and the security traces together cover and prevent tampering with the electronic circuitry of the printed circuit board.
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