Importance

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Abstract

According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+ diffusion region. The semiconductor structure further includes an N well ring situated between the NFET and the P+ substrate tie ring, where the N well ring increases snap-back conduction uniformity in the NFET. The semiconductor structure further includes an N+ active ring situated between the NFET and the P+ substrate tie ring, where the N+ active ring surrounds the NFET and connects the P+ substrate tie ring to the N well ring. The N+ active ring includes a salicide layer situated on an N+ diffusion region, where the salicide layer of the N+ active ring connects the N well ring to the P+ substrate tie ring.

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First Claim