Dual-SiGe epitaxy for MOS devices
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United States of America Patent
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Jul 6, 2010
Grant Date -
Jun 5, 2008
app pub date -
Dec 5, 2006
filing date -
Dec 5, 2006
priority date (Note) -
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Abstract
A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.
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