Efficient rounding circuits and methods in configurable integrated circuit devices
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 24, 2011
Grant Date -
N/A
app pub date -
Feb 9, 2010
filing date -
Feb 9, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A specialized processing block for a configurable integrated circuit device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry reuses an adder that is also available, in other configurations, for accumulation of the result. Rounding is performed by adding a constant to the result and then truncating at the bit position at which rounding is desired. The constant may be entered by a user, or may be derived based on a desired rounding method from mask data entered by the user to identify the rounding bit position.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully