M1 testable addressable array for device parameter characterization
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United States of America Patent
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Mar 31, 2009
Grant Date -
Oct 30, 2008
app pub date -
Apr 26, 2007
filing date -
Apr 26, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more arrays disposed between two of the plurality of pads. The integrated circuit device further includes one or more n-bit decoders, each disposed between two of the plurality of pads and electrically coupled to a corresponding one of the one or more arrays. Each n-bit decoder comprises one or more outputs that deliver a defined voltage to each device under test in the corresponding one of the one or more arrays of devices under test. The integrated circuit device and corresponding electrical connections are implemented in a single level of metal.
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