Pipelined successive approximation register analog-to-digital converter and method of analog-to-digital conversion
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United States of America Patent
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Oct 19, 2021
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Mar 18, 2021
app pub date -
Sep 16, 2020
filing date -
Sep 17, 2019
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Abstract
A pipelined successive approximation register analog-to-digital converter (2), SAR ADC, comprises a first SAR ADC stage (4); an inter-stage amplifier (6) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage (8) input from the inter-stage amplifier, wherein the inter-stage amplifier (6) comprises one or more MOS transistors (16, 18), wherein the source and drain terminals of each of the one or more MOS transistors (16, 18) are connected to each other and may be toggled between ground and a supply voltage.
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